Version:                        0x00030600
Trusted:                        0x00000000
Issue Date:                     0x27032024		; today's date
OEM UniqueID:                   0x4D52564C		; MRVL
Stepping:                       0x00000000
Processor Type:                 <undefined>		; ARMADA3700
Boot Flash Signature:           0x55415223		; Select UAR'23
Number of Images:               3
Size of Reserved in bytes:      36

Image ID:                       0x54494D48		; TIMH
Next Image ID:                  0x57544d49		; WTMI next
Flash Entry Address:            0x00000000		; TIM flash addr
Load Address:                   0x20006000		; TIM ISRAM addr
Image Size To CRC in bytes:     0xFFFFFFFF
Hash Algorithm ID:              32			; SHA-256
Partition Number:               0
Image Filename: TIM_ATF.bin

Image ID:                       0x57544d49		; WTMI
Next Image ID:                  0x4F424d49		; OBMI next
Flash Entry Address:            0x00004000		; WTMI flash addr
Load Address:                   0x1FFF0000		; WTMI RAM addr
Image Size To CRC in bytes:     0xFFFFFFFF
Hash Algorithm ID:              32			; SHA-256
Partition Number:               0
Image Filename: /home/runner/work/omr/espressobin/5.4/source/staging_dir/target-aarch64_cortex-a53_musl/image/a3700-utils/wtmi/build/wtmi.bin

Image ID:                       0x4F424d49		; OBMI
Next Image ID:                  0xFFFFFFFF		; NONE
Flash Entry Address:            0x00015000		; OBMI flash addr
Load Address:                   0x64100000		; OBMI RAM addr
Image Size To CRC in bytes:     0xFFFFFFFF
Hash Algorithm ID:              32			; SHA-256
Partition Number:               0
Image Filename: /home/runner/work/omr/espressobin/5.4/source/build_dir/target-aarch64_cortex-a53_musl/trusted-firmware-a-espressobin-v7-2gb/trusted-firmware-a-2.4/build/a3700/release/boot-image.bin

Reserved Data:
0x4F505448	;OPTH
0x00000002	; Number of Reserved Packages
0x43525632	;CRV2
0x00000014	; Size of CRV2 package in bytes
0x00000001	; Number of cores to release
0x00000002	; Core_ID: 0 - AP0, 1 - AP1, 2 - CM3
0x1fff06f0	; PC address for Core_ID above
0x5465726D	;Term
0x00000008	; Size of this package in bytes

Extended Reserved Data:
Consumer ID:
CID: TBRI
PID: GPP1
PID: GPP2
PID: DDR3
End Consumer ID:
GPP:
GPP_PID: GPP1
GPP Operations:
GPP_IGNORE_INST_TO: 0x0
End GPP Operations:
Instructions:
TEST_ADDR_AND_BRANCH: 0xC000D00C 0x80000000 0x00000000 == BPS1
AND_VAL: 0xC000D00C 0x7FFFFFFF
WRITE: 0xC0013840 0x00001D1E
LABEL: BPS0
NOP:
BRANCH: BPS0
LABEL: BPS1

; A3700 IO configuration
; On A3700 DB north bridge VDDO_PIO and VDDO_SIO are 1.8V, VDDO_JIO is 2.5V.
AND_VAL: 0xC0015600 0xFFFFFEFF
OR_VAL: 0xC0015600 0x00000600
; On A3700 DB south bridge GBE core voltage is 2.5V.
OR_VAL: 0xC001A400 0x00000040
End Instructions:
End GPP:
GPP:
GPP_PID: GPP2
GPP Operations:
GPP_IGNORE_INST_TO: 0x0
End GPP Operations:
Instructions:
; Check the status of counter #3, if the counter is inactive,
; reenable the counter.
TEST_ADDR_AND_BRANCH: 0xC0008330 0x00000002 0x00000002 == CNT3
AND_VAL: 0xC0008330 0xFFFFFFFE
OR_VAL: 0xC0008330 0x00000001
LABEL: CNT3

; Clean the mailbox
TEST_ADDR_AND_BRANCH: 0xC001404C 0x00000001 0x00000001 == MB1
WRITE: 0x64000400 0x00000000
LABEL: MB1

; Set cpu dram window size
; When cs1 is not selected, cpu dram window size is just dram cs0's size,
; and window base address is 0 as cs0 memory always starts from 0;
; when dram cs1 is selected, the cpu dram window is the combination of cs0 and cs1,
; the window base address is still 0 while the window size is the sum of cs0's size and cs1's size,
; and since cs0 and cs1 are in succession, then cs1's start address is just cs0's size,
; so in this case the cpu dram window size is the sum of cs1's start addess and cs1's size.

TEST_ADDR_AND_BRANCH: 0xC0000208 0x00000001 0x00000001 == CS1
LOAD_SM_ADDR: SM0 0xC0000200	; load reg of Channel 0 MMAP CS Low to SM0
LOAD_SM_VAL: SM1 0x00000000	; the 64KB number of cs0 memory starting address is always 0
BRANCH: CONF

LABEL: CS1
LOAD_SM_ADDR: SM0 0xC0000208	; load reg of Channel 1 MMAP CS Low to SM0
MOV_SM_SM: SM1 SM0		; SM1 = SM0
AND_SM_VAL: SM1 0xFF800000	; MEM_START_ADDR_L_SHIFT = 23, get Starting cs1 memory starting address
RSHIFT_SM_VAL: SM1 0x00000010	; count the 64KB number of cs1 memory starting address

LABEL: CONF
RSHIFT_SM_VAL: SM0 0x00000010	; AREA_LEN_SHIFT = 16
AND_SM_VAL: SM0 0x0000001F	; &= AREA_LEN_SHIFT
; count current cs dram size value in window size format,
; the number of 1s specifies the size of the window in 64 KB granularity,
; dram size value = (1 << AREA_LEN) - 1;
LOAD_SM_VAL: SM2 0x00000001
LABEL: CON
TEST_SM_AND_BRANCH: SM0 0x0000001F 0x00000000 == OUT
LSHIFT_SM_VAL: SM2 0x00000001
SUB_SM_VAL: SM0 0x00000001
BRANCH: CON
LABEL: OUT
SUB_SM_VAL: SM2 0x00000001
; finish current cs dram size value counting;
ADD_SM_SM: SM2 SM1		; count total dram size value in window size format
; Because Armada 37x0's 4G address space includes an "internal register" window,
; its cpu dram window size is up to 2 GB;
; So when total dram size is more than 2GB, only 2GB is configured in the first cpu dram window,
; the remain dram sizes are configured in other cpu dram windows in atf later;
; Window size value's valid bits are bits[23:0];
; When total dram size is 2GB, the value in window size format will be 0x7FFFF;
; when total dram size is more than 2GB, some continuous left bits of 0x7FFFF will be set,
; the left bits mask is 0xFF8000.
TEST_SM_AND_BRANCH: SM2 0x00FF8000 0x00000000 == DRAM
LOAD_SM_VAL: SM2 0x00007FFF
LABEL: DRAM
AND_VAL: 0xC000CF00 0xFFFFFFFE	; disable cpu dram window
STORE_SM_ADDR: SM2 0xC000CF04	; write cpu dram window size
OR_VAL: 0xC000CF00 0x00000001	; enable cpu dram window
End Instructions:
End GPP:
DDR Initialization:
DDR_PID: DDR3
Operations:
DDR_INIT_ENABLE: 0x00000001
End Operations:
Instructions:
; Switch all clocks to REFCLOCK
WRITE: 0XC0013010 0x00000000
; TBG-A: SE vco_div 0x1,
; DIFF vco_div 0x1, vco_range 0xa
; tbg_N 0x30 KVCO = 1600 MHz
WRITE: 0xC0013204 0x00C00091
WRITE: 0xC0013204 0x00C000C1
WRITE: 0xC0013220 0x08030803
WRITE: 0xC0013208 0x94011401
WRITE: 0xC0013230 0x00020002
WRITE: 0xC0013208 0x94011401
WRITE: 0xC001320C 0x53E556E6
WRITE: 0xC0013210 0x014A014A
WRITE: 0xC001320C 0x53E556E5
WRITE: 0xC0013204 0x00C000C0
WRITE: 0xC0013208 0x94011401
WAIT_FOR_BIT_SET: 0xC0013208 0x80008000 0x00100000
DELAY: 0x00000100

; Set clocks to DDR400 preset
WRITE: 0xC0013014 0x07032018
WRITE: 0xC0013004 0x1296202C
WRITE: 0xC0013008 0x21061AA9
WRITE: 0xC001300C 0x20543084
WRITE: 0xC0013000 0x0003C0F2

WRITE: 0xC0013210 0x014B014A
; Switch all clocks to back dividers
WRITE: 0xC0013010 0x00009FFF
DELAY: 0x00000001

; Set DDR4 to 800MHz
; Pre-init
WRITE: 0xC0014008 0x00404500
WRITE: 0xC0002000 0x00010000
WRITE: 0xC0002004 0x00000000
; DDR MAC init
WRITE: 0xC0000340 0x00000303
WRITE: 0xC0000344 0x0200000A
WRITE: 0xC0000310 0x00100000
WRITE: 0xC0000314 0x00100000
WRITE: 0xC0000304 0x00000400
WRITE: 0xC0000308 0x00000000
WRITE: 0xC0000044 0x00030200
WRITE: 0xC00002C0 0x00006000
WRITE: 0xC00002C4 0x00100030
WRITE: 0xC0000058 0x0000143F
WRITE: 0xC0000048 0x00000001
WRITE: 0xC0000180 0x00010200
WRITE: 0xC0000050 0x000001FF
WRITE: 0xC000004C 0x00000000
WRITE: 0xC0000054 0x00000480
WRITE: 0xC0000300 0x00000B0C
WRITE: 0xC0000380 0x00061A80
WRITE: 0xC0000384 0x00027100
WRITE: 0xC0000388 0x00000050
WRITE: 0xC000038C 0x00000400
WRITE: 0xC0000390 0x00800200
WRITE: 0xC0000394 0x011803CF
WRITE: 0xC0000398 0x01200255
WRITE: 0xC000039C 0x00000808
WRITE: 0xC00003A0 0x04050500
WRITE: 0xC00003A4 0x00000002
WRITE: 0xC00003A8 0x00001808
WRITE: 0xC00003AC 0x1C250C1A
WRITE: 0xC00003B0 0x0C0C060C
WRITE: 0xC00003B4 0x05040602
WRITE: 0xC00003B8 0x00000605
WRITE: 0xC0000200 0x000E0001
WRITE: 0xC0000204 0x00000000
WRITE: 0xC0000220 0x05020635
WRITE: 0xC0000208 0x400E0001
WRITE: 0xC000020C 0x00000000
WRITE: 0xC0000224 0x05020635
WRITE: 0xC00003C0 0x00020205
WRITE: 0xC00003C4 0x00000003
WRITE: 0xC00003DC 0x00081239
WRITE: 0xC00002C8 0x00000000
WRITE: 0xC0000064 0x00000006
; DDR PHY init
WRITE: 0xC0001010 0x00100100
WRITE: 0xC0001014 0x00080200
WRITE: 0xC000101C 0x90118011
WRITE: 0xC0001028 0x00000011
WRITE: 0xC0001040 0x00000607
WRITE: 0xC00010C0 0x51000000
WRITE: 0xC0001050 0x15150000
WRITE: 0xC0001054 0x20100000
WRITE: 0xC0001074 0x15150000

;Setp7: init read fifo pointer and OFF spec parameter
WRITE: 0xC0001000 0x00004032
WRITE: 0xC00003bc 0x02020404

;Step8: phyinit_sequence_sync2(1, 3, 2, 0)
WRITE: 0xC0001014 0x00080200
OR_VAL: 0xC0001038 0x00000003
WRITE: 0xC000103C 0x00000020
WRITE: 0xC0001020 0x80000000
WRITE: 0xC0001020 0x20000000
WRITE: 0xC0001020 0x40000000
DELAY: 0x0000000A
WRITE: 0xC0001020 0x80000000
DELAY: 0x0000000A

;Step9: DDRPHY Driver/Receiver & DQS internal Pullup/Pulldown settings
WRITE: 0xC0001004 0xD0677449
WRITE: 0xC0001008 0xC770055A
WRITE: 0xC000100C 0x5461DF77

;Step10:Skip for DDR4

;Step11: DDRPHY pads POWERDOWN disable
WRITE: 0xC0001030 0x03800000
WRITE: 0xC0001034 0x00000000
WRITE: 0xC0001090 0x00000004
WRITE: 0xC0001094 0x00000000

;Step12: initC2Dofset DDR4
WRITE: 0xC00010E0 0x00010001
WRITE: 0xC00010D0 0x000C0300
WRITE: 0xC00010D4 0x00300C03
WRITE: 0xC00010D8 0x00300C03
WRITE: 0xC00010DC 0x00300C03
WRITE: 0xC00010E0 0x00010002
WRITE: 0xC00010D0 0x000C0300
WRITE: 0xC00010D4 0x00300C03
WRITE: 0xC00010D8 0x00300C03
WRITE: 0xC00010DC 0x00300C03
WRITE: 0xC00010E0 0x00010004
WRITE: 0xC00010D0 0x000C0300
WRITE: 0xC00010D4 0x00300C03
WRITE: 0xC00010D8 0x00300C03
WRITE: 0xC00010DC 0x00300C03
WRITE: 0xC00010E0 0x00010008
WRITE: 0xC00010D0 0x000C0300
WRITE: 0xC00010D4 0x00300C03
WRITE: 0xC00010D8 0x00339CE7
WRITE: 0xC00010DC 0x00300C03
WRITE: 0xC00010E0 0x00010010
WRITE: 0xC00010D0 0x000C0300
WRITE: 0xC00010D4 0x00300C03
WRITE: 0xC00010D8 0x00339CE7
WRITE: 0xC00010DC 0x00300C03

;for CS1
WRITE: 0xC00010E0 0x00020001
WRITE: 0xC00010D0 0x000C0300
WRITE: 0xC00010D4 0x00300C03
WRITE: 0xC00010D8 0x00300C03
WRITE: 0xC00010DC 0x00300C03
WRITE: 0xC00010E0 0x00020002
WRITE: 0xC00010D0 0x000C0300
WRITE: 0xC00010D4 0x00300C03
WRITE: 0xC00010D8 0x00300C03
WRITE: 0xC00010DC 0x00300C03
WRITE: 0xC00010E0 0x00020004
WRITE: 0xC00010D0 0x000C0300
WRITE: 0xC00010D4 0x00300C03
WRITE: 0xC00010D8 0x00300C03
WRITE: 0xC00010DC 0x00300C03
WRITE: 0xC00010E0 0x00020008
WRITE: 0xC00010D0 0x000C0300
WRITE: 0xC00010D4 0x00300C03
WRITE: 0xC00010D8 0x00339CE7
WRITE: 0xC00010DC 0x00300C03
WRITE: 0xC00010E0 0x00020010
WRITE: 0xC00010D0 0x000C0300
WRITE: 0xC00010D4 0x00300C03
WRITE: 0xC00010D8 0x00339CE7
WRITE: 0xC00010DC 0x00300C03

;Step 13: Set DDRPHY read DAC default VREF/range value
LOAD_SM_ADDR: SM0 0xC0001038
AND_SM_VAL: SM0 0xFFCAFFFF
OR_SM_VAL: SM0 0x00150000
STORE_SM_ADDR: SM0 0xC0001038
LOAD_SM_ADDR: SM0 0xC0001038
AND_SM_VAL: SM0 0xC0FFFFFF
OR_SM_VAL: SM0 0x32000000
STORE_SM_ADDR: SM0 0xC0001038
LOAD_SM_ADDR: SM0 0xC0001038
AND_SM_VAL: SM0 0x3FFFFFFF
OR_SM_VAL: SM0 0x40000000
STORE_SM_ADDR: SM0 0xC0001038
DELAY: 0x00000001

;Step 17: Set default value for DRAM DQ VREF
OR_VAL: 0xC0000308 0x00000010
OR_VAL: 0xC000030C 0x00800001
WRITE: 0xC0000028 0x13004000
LOAD_SM_ADDR: SM0 0xC000030C
DELAY: 0x00000001
AND_SM_VAL: SM0 0xFFC0FFFF
OR_SM_VAL: SM0 0x250000
STORE_SM_ADDR: SM0 0xC000030C
WRITE: 0xC0000028 0x13004000
DELAY: 0x00000001
AND_VAL: 0xC0000308 0xFFFFFFEF
WRITE: 0xC0000028 0x13004000
DELAY: 0x00000001

;Step18: Trigger DDR init for both CS
WRITE: 0xC0000020 0x13000001

;Step19: Poll and wait for ddr init done
WAIT_FOR_BIT_SET: 0xC0000008 0x00000001 0x00001000
WAIT_FOR_BIT_SET: 0xC0000008 0x00000010 0x00001000
; DDR INIT DONE

LOAD_SM_VAL: SM0 0

LABEL: LP1
LOAD_SM_ADDR: SM2 0xC000030C
AND_SM_VAL: SM2 0xFFC0FFFF
MOV_SM_SM: SM1 SM0
LSHIFT_SM_VAL: SM1 0x10
OR_SM_SM: SM2 SM1
STORE_SM_ADDR: SM2 0xC000030C
OR_VAL: 0xC0000028 0x13004000
ADD_SM_VAL: SM0 0x1
TEST_SM_AND_BRANCH: SM0 0x000000FF 0x00000032 < LP1

AND_VAL: 0xC0000308 0xFFFFFFEF
OR_VAL: 0xC0000028 0x13004000
OR_VAL: 0xC0000308 0x00000010
OR_VAL: 0xC000030C 0x00800001
WRITE: 0xC0000028 0x13004000
DELAY: 0x00000001

LOAD_SM_ADDR: SM2 0xC000030C
AND_SM_VAL: SM2 0xFFC0FFFF
OR_SM_VAL: SM2 0x00250000
STORE_SM_ADDR: SM2 0xC000030C
WRITE: 0xC0000028 0x13004000
DELAY: 0x00000001

AND_VAL: 0xC0000308 0xFFFFFFEF
WRITE: 0xC0000028 0x13004000
DELAY: 0x00000001
End Instructions:
End DDR Initialization:
End Extended Reserved Data:

